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73s8024rn low - cost smart card interface data sheet rev. 2 1 19 - 5 404; rev 2 ; 6 / 1 2 description the 73s8024rn is a single smart card (icc) interface ic that can be controlled by a dedicated control bus . the 73s8024rn has been designed to provide full electrical compliance with iso 7816- 3, emv 4.0 (emv2000) and nds specificati ons. interfacing with the system controller is done through a control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. the card clock can be generated by an on- chip oscillator using an external crystal or by connection to a clock signal. the 73s8024rn incorporates an iso 7816- 3 activation/deactivation sequencer that controls the card signals . level - shifters drive the card signals with the selected card voltage (3v or 5v), coming from an internal low drop - out (ldo) voltage regulator . this ldo regulator is powered by a dedicated power supply input v pc . digital circuitry is separately powered by a digital power supply v dd . with its embedded ldo regulator, the 73s8024rn is a cost effective solution for any application where a 5v (typically - 5% +10%) power supply is available. hardware support for auxiliary i/o lines, c4 / c8 contacts, is provided*. emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry . the fault can be a card over - current, a v dd (digital power supply)**, a v pc (regulator power supply), a v cc (card power supply) or an over - heating fault. the card over - current circuitry is a true curr ent detection function, as opposed to v cc voltage drop detection, as usually implemented in icc interface ics. the v dd voltage fault has a threshold voltage that can be adjusted with an external resistor or resistor network . it allows automated card deactivation at a customized v dd voltage threshold value . it can be used, for instance, to match the system controller operating voltage range. applications ? set - top- box conditional access and pay - per - view ? point of sa les and transaction terminals ? control access and identificatio n * pin s/functions not available on 20 - pin qfn package. ** user v dd_flt threshold configuration not available on 20- pin qfn package. advantages ? traditional step - up converter is replaced by a ldo regulator: ? greatly reduced power diss ipation ? fewer external components are required ? better noise performance ? high current capability (90ma supplied to the card) ? so28 package is p in-to - pin compatible with industry - standard tda8004 and tda8024 ? card clock stop (high and low) mode ? small for mat (4x4x0.85mm) 20qfn package option ? true card over - current detection features ? card interface: ? complies with iso 7816- 3, emv 4.0 , and nds ? an ldo voltage regulator provides 3v / 5v to the card from an external power supply input ? provides at least 90ma to the card ? iso 7816- 3 activation / deactivation sequencer with e mergency automated deactivation on card removal or fault detected by the protection circuitry ? protection includes 3 voltage supervisors that detect voltage drops on v cc (card), v dd (digital)** , and v pc (regulator) power supplies ? the v dd voltage supervisor threshold value can be externally adjusted** ? o ver - current detection 150ma max ? card clock stop high or low* ? 2 card detection inputs, 1 for each possible user polarity ? auxiliary i/o lines, for c 4 / c8 contact signals* ? card clk clock frequency up to 20mhz ? system controller interface: ? 3 d igital inputs control the card activation / deactivation, card reset and card voltage ? 4 digital inputs control the card clock (division rate and card clock stop mo des) ? 1 digital output, interrupt to the system controller, allows the system controller to monitor the card presence and faults . ? crystal oscillator or host clock, up to 27mhz ? regulator power supply: ? 4.75v to 5.5v (emv 4.0) ? 4.85v to 5.5v (nds) ? digital inte rfacing: 2.7v to 5.5v ? 6kv esd protection on the card interface ? package: so28, 20qfn or 32qfn
73s8024rn data sheet ds_8024rn_020 2 rev. 2 functional diagram pin numbers reference the 28 so package . [pin numbers] reference the 32 qfn package . {pin numbers} reference the 20 qfn package. figure 1 : 73s8024rn block diagram icc i / o buffers digital power supply vdd voltage supervisor voltage reference xtal osc clock generation digital circuitry & fault logic v dd fault v cc fault v pc fault int _ clk vdd vpc vcc rst clk pres pres xtalin xtalout clkdiv 1 clkdiv 2 gnd temp fault clkstop { 18 } [ 29 ] 1 { 19 } [ 30 ] 2 { 20 } [ 31 ] 3 5 [ 2 , 9 , 16 , 25 , 32 ] 6 [ 4 ] 7 9 [ 6 ] { 3 } 10 [ 7 ] { 4 } 11 [ 8 ] { 5 } 12 [ 10 ] 13 [ 11 ] 14 [ 12 ] { 6 } 15 [ 13] { 7 } 17 [ 15 ] { 9 } 16 [ 14 ] { 8 } 21 [ 20] { 12} { 11 } [ 19 ] 20 { 10 } [ 18 ] 19 18 [ 17 ] { 17 } [ 26 ] 26 { 16 } [ 24 ] 25 { 15 } [ 23 ] 24 { 14 } [ 22 ] 23 [ 28 ] 28 [ 27 ] 27 { 13 } [ 21 ] 22 iso - 7816 sequencer r - c osc . ldo regulator & voltage supervisors icc reset buffer icc clock buffer over temp clklev i / o aux 1 aux 2 i / ouc aux 1 uc aux 2 uc gnd vddf _ adj rstin cmdvcc 5 v / 3 v off [ 5 ] 8 gnd 4 [ 1 ] { 1 } nc 6 [ 3 ] { 2 } i cc fault
ds_8024rn_020 73s8024rn data sheet rev. 2 3 table of contents 1 pin description ...............................................................................................................................5 2 system controller interface ...........................................................................................................7 3 power supply and voltage supervision ........................................................................................8 4 card power supply ........................................................................................................................9 5 over - temperature monit or .............................................................................................................9 6 on- chip oscillator and card clock ...............................................................................................9 7 activation sequence .................................................................................................................... 10 8 deactivation sequence ................................................................................................................ 12 9 off and fault detection .............................................................................................................. 13 10 i/o circuitry and timing ............................................................................................................... 13 11 typical application schematic .................................................................................................... 15 12 electrical specification ................................................................................................................ 16 12.1 absolute maximum ratings .................................................................................................... 16 12.2 recommended operating conditions ..................................................................................... 16 12.3 package thermal parameters ................................................................................................ 16 12.4 smart card interface requirements ........................................................................................ 17 12.5 characteristics: digital signals ................................................................................................ 19 12.6 dc characteristics .................................................................................................................. 20 12.7 voltage / temperature fault detection circuits ....................................................................... 20 13 mechanical drawing (20qfn) ...................................................................................................... 21 14 package pin designation (20qfn) ............................................................................................... 22 15 mechanical drawing (32qfn) ...................................................................................................... 23 16 package pin designation (32qfn) ............................................................................................... 24 17 mechanical drawing (so) ............................................................................................................. 25 18 package pin designation (so) ..................................................................................................... 25 1 9 ordering information .................................................................................................................... 26 20 related documentation ................................................................................................................ 26 21 contact information ..................................................................................................................... 26 revision history ................................................................................................................................... 27
73s8024rn data sheet ds_8024rn_020 4 rev. 2 figures figure 1: 73s8024rn block diagram ...................................................................................................... 2 figure 2: activation sequence C rstin low when cmdvcc goes low .............................................. 10 figure 3: activation sequence C rstin high when cmdvccb goes low ........................................... 11 figure 4: deac tivation sequence ........................................................................................................... 12 figure 5: timing diagram C management of the interrupt line off ....................................................... 13 figure 6: i/o and i/ouc state diagram ................................................................................................. 14 figure 7: i/o C i/ouc delays timing diagram ....................................................................................... 14 figure 8: 73s8024rn C typical application schematic .......................................................................... 15 figure 9: 20qfn mechanical drawing ................................................................................................... 21 figure 10: 20qfn pin out ..................................................................................................................... 22 figure 11: 32qfn mechan ical drawing ................................................................................................. 23 figure 12: 32qfn pin out ..................................................................................................................... 24 tables table 1: choice of v cc pin capacitor ....................................................................................................... 9 table 2: card clock frequency ............................................................................................................... 9
ds_8024rn_020 73s8024rn data sheet rev. 2 5 1 pin description card interface na me pin 28so pin 20qfn pin 32qfn description i/o 11 5 8 card i/o: data signal to/from card. includes a pull - up resistor to v cc. aux1 13 C 11 aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 12 C 10 aux2: auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 16 8 14 card reset: provides reset (rst) signal to card. clk 15 7 13 card clock: provides clock signal (clk) to card. the rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on xtalin and clkdiv selections. pres 10 4 7 card pres ence switch: active high indicates card is present . should be tied to gnd when not used, but it includes a high - impedance pull - down current source. pres 9 3 6 card presence switch: active low indicates card is present . should be tied to v dd when not use d, but it includes a high - impedance pull - up current source. vcc 17 9 15 card power supply C logically controlled by sequencer, output of ldo regulator . requires an external filter capacitor to the card gnd . gnd 14 6 12 card ground . miscellaneous input s and o utputs n ame pin 28so pin 20qfn pin 32qfn d escription xtalin 24 15 23 crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. xtalout 25 16 24 crystal oscillator output: connected to crystal. left ope n if xtalin is being used as external clock input. vddf_adj 18 C 17 v dd fault threshold adjustment input: this pin can be used to adjust the v ddf values (that controls deactivation of the card). must be left open if unused. nc 5 C 2, 9, 16, 25, 32 non - c onnected pin. power supply and ground n ame pin 28so pin 20qfn pin 32qfn d escription vdd 21 12 20 system interface supply voltage and supply voltage for internal circuitry. vpc 6 2 3 ldo regulator power supply source. gnd 4 1 1 ldo regulator ground. gnd 22 13 21 digital ground.
73s8024rn data sheet ds_8024rn_020 6 rev. 2 microcontroller interface n ame pin 28so pin 20qfn pin 32qfn description cmdvcc 19 10 18 command vcc (negative assertion): logic low on this pin causes the ldo regulator to ramp the v cc supply to the card and initiates a car d activation sequence, if a card is present. 5v /#v 3 20 31 5 volt / 3 volt card selection: logic one selects 5 volts for v cc and card interface, logic low selects 3 volt operation. when the part is to be used with a single card voltage, this pin should be tied to either gnd or v dd . however, it includes a high impedance pull - up resistor to default this pin high (selection of 5v card) when not connected. clkstop 7 C 4 stops the card clock signal during a card session when set high (card clock stop mode) . internal pull - down resistor allows this pin to be left as an open circuit if the clock stop mode is not used. clklvl 8 C 5 sets the logic level of the card clock stop mode when the clock is de - activated by setting pin 7 high. logic low selects card sto p low . logic high selects card stop high . internal pull - down resistor allows this pin to be left as an open circuit if the clock stop mode is not used. clkdiv1 clkdiv2 1 2 18 19 29 30 sets the divide ratio from the xtal oscillator (or external clock in put) to the card clock. these pi ns include pull - down resistors. clkdiv1 clkdiv2 clock rate 0 0 xtalin/8 0 1 xtalin/4 1 1 xtalin/2 1 0 xtalin off 23 14 22 interrupt signal to the processor. active low - multi - function indicatin g fault conditions and card presence. o pen drain output configuration. it includes an internal 21k pull - up to v dd. rstin 20 11 19 reset input: this signal is the reset command to the card. i/ouc 26 17 26 system controller data i/o to/from the card. in cludes a pull - up resistor to v dd. aux1uc 27 C 27 system controller auxiliary data i /o to/from the card. includes a pull - up resistor to v dd. aux2uc 28 C 28 system controller auxiliary data i/o to/from the card. includes a pull - up resistor to v dd.
ds_8024rn_020 73s8024rn data sheet rev. 2 7 2 syste m controller interface three separated digital inputs allow direct control of the card interface from the host as follows: ? pin cmdvcc : when low, starts an activation sequence . ? pin rstin: controls the card reset signal (when enabled by the sequencer) . ? pin 5v/ #v : defines the card voltage . card clock is controlled by four digital inputs: ? clkdiv1 and clkdiv2 define the division rate for the clock frequency, from the input clock frequency (crystal or external clock) . ? clkstop (active high) allows card power do wn mode by stopping the card clock . ? clklev defines the card clock level of the card power down mode. interrupt output to the host: as long as the card is not activated, the off pin informs the host about the card presence only (low = no card in the reader ). when cmdvcc is set low (card activation sequence requested from the host), low level on off means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over - current fault) that automatically initiates a deacti vation sequence.
73s8024rn data sheet ds_8024rn_020 8 rev. 2 3 power supply and voltage supervision the 73s8024rn smart card interface ic incorporates a ldo voltage regulator . the voltage output is controlled by the digital input 5v/ #v . this regulator is able to provide either 3v or 5v card voltage from the power supply applied on the vpc pin. digital circuitry is powered by the power supply applied on the vdd pin . v dd also defines the voltage range to interface with the system controller. three voltage supervisors constantly check the presence o f the voltages v dd , v pc and v cc . a card deactivation sequence is forced upon fault of any of these voltage supervisors . the two voltage supervisors for v pc and v cc are linked so that a fault is generated to activate a deactivation sequence when the volta ge v pc becomes lower than v cc . it allows the 73s8024rn to operate at lower v pc voltage when using 3v cards only. the voltage regulator can provide a current of at least 90ma on v cc that comply easily with emv 4.0 and nds specifications . the v pc voltage supervisor threshold values are defined from applicable standards (emv and nds). a third voltage supervisor monitors the v dd voltage . it is used to initialize the iso 7816- 3 sequencer at power - on, and to deactivate the card at power - off or upon fault . t he voltage threshold of the v dd voltage supervisor is internally set by default to 2.3v nominal . however, it may be desirable, in some applications, to modify this threshold value . the pin vddf_adj (pin 18 in the so package, pin 17 in the 32qfn package, not supported in the 20qfn package) is used to connect an external resistor r ext to ground to raise the v dd fault voltage to another value v ddf . the resistor value is defined as follows: r ext = 56k /(v ddf - 2.33) an alternative method (more accurate) of adjusting the v dd fault voltage is to use a resistive network of r3 from the pin to supply and r1 from the pin to ground (see applications diagram). in order to set the new threshold voltage, th e equivalent resistance must be determined. this resistance value will be designated kx. kx is defined as r1/(r1+r3). kx is calculated as: kx = (2.789 / v th ) - 0.6125 where v th is the desired new threshold voltage. to determine the values of r1 and r3 , use the following formulas. r3 = 24000 / kx r1 = r3*(kx / (1 C kx)) taking the example above, where a v dd fault threshold voltage of 2.7v is desired, solving for kx gives: ? kx = (2. 789 / 2.7) - 0.6125 = 0.42046. solving for r3 gives: ? r3 = 240 00 / 0.42046 = 57080. solving for r1 gives: ? r1 = 57080 *(0.4 2046 / (1 C 0.42046)) = 41412. using standard 1 % resistor values gives r3 = 57.6k : and r1 = 42.4k : these values give an equivalent resistance of kx = 0.4228, a 0.6% error. if the 2.3v default t hreshold is used, this pin mu st be left unconnected. the 20 qfn package has the v dd fault threshold fixed at this default value.
ds_8024rn_020 73s8024rn data sheet rev. 2 9 4 c ard p ower s upply the card power supply is internally provided by the ldo regulator, and controlled by the digital iso 7816- 3 sequencer . card voltage selection is carried out by the digital input 5v/ #v . choice of the v cc c apacitor: depending on the applications, the requirements in terms of both v cc minimum voltage and transient currents that the interface must be able to p rovide to the card are different . an external capacitor must be connected between the vcc pin and to the card ground in order to guarantee stability of the ldo regulator, and to handle the transient requirements . the type and value of this capacitor can be optimized to meet the desired specification . table 1 shows the recommended capacitors for each v pc power supply configuration and applicable specification. table 1 : choice of v cc pin capacitor specification requirements system requirements specification min v cc voltage allowed during transient c urrent max t ransient current c harge min v pc power supply r equired capacitor type capacitor value emv 4.0 4.6v 30na.s 4.75v x5r/x7r w/ esr < 100m ? 3.3 f iso 7816 - 3 4.5v 20na.s 4.75v 1 f nds 4.6v 40na.s 4.85v 1 f note: capacitor value for nds implementation is also defined by the deactivation time requirement. 5 o ver - t emperature m onitor a built - in detector monitors die temperature . upon an over - temperature condition, a card dea ctivation sequence is initiated, and an error or fault condition is reported to the system controller. 6 on - c hip o scillator and c ard c lock the 73s8024rn device has an on - chip oscillator that can generate the smart card clock using an external crystal (conne cted between the pins xtalin and xtalout) to set the oscillator frequency . when the clock signal is available from another source, it can be connected to the pin xtalin, and the pin xtalout should be left unconnected. the card clock f requency may be chos en between four different division rates, defined by digital inputs clkdiv 1 and clkdiv 2, as per table 2. table 2 : card clock frequency clkdiv1 clkdiv2 clk 0 0 ? xtalin 0 1 ? xtalin 1 0 xtalin 1 1 ? xtalin card power down mo de (card clock stop) is supported and is controllable through the dedicated digi tal inputs clkstop and clklev ( not supported in the 20qfn package).
73s8024rn data sheet ds_8024rn_020 10 rev. 2 7 a ctivation sequence the 73s8024rn smart card interface ic has an internal 10ms delay at power on reset or o n the application of v dd > v ddf . no activation is allowed at this time. the cmdvcc (edge triggered) must then be set low to activate the card. in order to initiate activation, the card must be present; there can be no over - temperature fault or no v dd f ault. the following steps show the activation sequence and the timing of the card control signals when the system controller sets cmdvcc low while the rstin is low: ? cmdvcc is set low. ? next, the internal v cc control circuit checks the presence of v cc at t he end of t 1 . in normal operation, the voltage v cc to the card becomes valid during t 1 . if v cc does not become valid, the off goes low to report a fault to the system controller, and the power v cc to the card is shut off. ? turn i/o (aux1, aux2) to recepti on mode at the end of (t 2 ). ? clk is applied to the card at the end of (t 3 ). ? rst is a copy of rstin after (t 4 ). rstin may be set high before t 4 , however the sequencer will not set rst high until 42000 clock cycles after the start of clk. cmdvcc vcc i/o clk rstin t 1 t 2 t 3 t 4 rst t 1 = 0.510 ms (timing by 1.5mhz internal oscillator) t 2 = 1.5 s, i/o goes to reception state t 3 = >0.5 s, clk starts t 4 42000 card clock cycles . time for rst to become the copy of rstin figure 2 : activation sequence C rstin low w hen cmdvcc goes l ow
ds_8024rn_020 73s8024rn data sheet rev. 2 11 the following steps show the activation sequence and the timing of the card control signals when the system controller pulls the cmdvcc low while the rstin is high: ? cmdvcc is set low. ? next, the internal v cc control circuit checks the presence of v cc at the end of t 1 . in normal operation, the voltage v cc to the card becomes valid during this time . if not, off goes low to report a fault to the system controller, and the power v cc to the card is shut down. ? due to the fall of rstin at (t 2 ), turn i/o (aux1, aux2) to reception mode. ? clk is applied to the card at the end of (t 3 ), after i/o is in reception m ode. ? rst is to be a copy of rstin after (t 4 ). rstin may be set high before t 4 , however the sequencer will no t set rst high until 42000 clock cycles after the start of clk. cmdvcc vcc i/o clk rstin t 1 t 2 t 3 t 4 rst t 1 = 0.510 ms (timing by 1.5mhz internal oscillat or) t 2 = 1.5 s, i/o goes to reception state t 3 = > 0.5 s, clk active t 4 42000 card clock cycles. time for rst to become the copy of rstin figure 3 : activation sequence C rstin high w hen cmdvccb goes l ow
73s8024rn data sheet ds_8024rn_020 12 rev. 2 8 d eactivation s equence deactivation is initiated either by the system controller by setting the c mdvcc high, or automatically in the event of hardware faults . hardware faults are over - current, overheating, v dd fault, v pc fault, v cc fault, and card extraction during the session . to be noted that v pc and v cc faults are linked together so that a fault is generated when v pc goes lower than v cc . the following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the cmdvcc high or off goes low due to a fault or card removal: ? rst goes low at the e nd of t 1 . ? clk is set low at the end of t 2 . ? i/o goes low at the end of t 3 . out of reception mode. ? v cc is shut down at the end of time t 4 . after a delay t 5 (discharge of the v cc capacitor), v cc is low. rst clk i/o vcc t 1 t 2 t 3 t 4 t 5 cmdvcc -- or -- off t 1 = > 0.5 s, timing by 1.5mhz internal oscillator t 2 = > 7.5 s t 3 = > 0.5 s t 4 = > 0.5 s t 5 = depends on v cc filter capacitor. for nds application, c f =1 f makes t 1 + t 2 + t 3 + t 4 + t 5 < 100 s figure 4 : deactivation sequence
ds_8024rn_020 73s8024rn data sheet rev. 2 13 9 off an d f ault d etection there are two different cases that the system controller can monitor the off signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. outside a card session: in this condition, cmdv cc is always high, off is low if the card is not present, and high if the card is present . because it is outside a card session, any fault detection will not act upon the off signal . no deactivation is required during this time. d uring a card session: cm dvcc is always low, and off falls low if the card is extracted or if any fault detection is detected . at the same time that off is set low, the sequencer starts the deactivation process. the figure 5 shows the timing diagram for the signals cmdvcc , pres, and off during a card session and outside the card session: pres off cmdvcc vcc outside card session within card session off is low by card extracted off is low by any fault within card session figure 5 : timing diagram C management of the interrupt line off 10 i/o c ircuitry and timing the states of the i/o, aux1, and aux2 pins are low after power on reset and they are in high when the activation sequencer turns on the i/o reception state . see the activation sequence section for more details on when the i/o reception is enabled . the states of i/ouc, aux1uc, and aux2uc are high after power on reset. within a card session and when the i/o reception state is turn on, the first i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line . when the input i/o line rising edge is detected then both i/o lines return to their neutral state. figure 6 shows the state diagram of how the i/o and i/ouc lines are managed to become input or output . the delay betw een the i/o signals is shown in figure 7.
73s8024rn data sheet ds_8024rn_020 14 rev. 2 neutral state i/ouc in i/o reception i/oicc in no yes no no no yes no yes i/o & not i/ouc i/ouc & not i/o i/ouc i/o yes yes figure 6 : i/o and i/ouc state diagram i/o i/ouc t i/o_hl t i/o_lh t i/ouc_hl t i/ouc_lh delay from i/o to i/ouc: t i/o_hl = 100ns t i/o_lh = 25ns delay from i/ouc to i/o: t i/ouc_hl = 100ns t i/ouc_lh = 25ns figure 7 : i/o C i/ouc delays timing diagram
ds_8024rn_020 73s8024rn data sheet rev. 2 15 11 typical a pplication schematic so28 see note 4 vdd clkstop_from_uc y1 crystal c2 22pf c1 nds & iso7816=1uf, emv=3.3uf see note 5 rstin_from_uc clkdiv2_from_uc clk track should be routed far from rst, i/o, c4 and c8. notes: 1) vdd = 2.7v to 5.5v dc. 2) vpc = 4.75v(emv, iso)/4.85(nds) to 5.5v dc 3) required if external clock from up is used. 4) required if crystal is used. y1, c2 and c3 must be removed if external clock is used. 5) optional. can be left open. 6)internal pull-up allows it to be left open if unused. 7) r1 and r3 are external resistors that adjust the vdd fault voltage. can be left open. i/ouc_to/from_uc r1 rext1 see note 1 card detection switch is normally closed vpc c6 100nf vdd external_clock_from uc c4 100nf c3 22pf aux1uc_to.from_uc see note 5 c5 10uf aux2uc_to/from_uc see note 3 see note 2 clklvl_from_uc vdd low esr (<100mohms) c1 should be placed near the sc connecter contact clkdiv1_from_uc cmdvcc_from_uc 73s8024rn 1 2 3 4 5 6 7 12 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 28 27 25 24 26 clkdiv1 clkdiv2 5v3v_ gnd nc vpc clkstop aux2 clklvl presb pres i/o aux1 gnd clk rst vcc vddf_adj cmdvcc_ rstin vdd gnd off_ aux2uc aux1uc xtalout xtalin i/ouc 5v/3v_select_from_uc off_interrupt_to_uc r3 rext2 - or - r2 20k see note 7 smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 see note 6 vdd figure 8 : 73s8024rn C typical application schematic
73s8024rn data sheet ds_8024rn_020 16 rev. 2 12 e lectric al specification 12.1 absolute maximum ratings operation outside these rating limits may cause permanent damage to the device. the smart card interface pins are protected against short circuits to v cc , ground, and each other. parameter rating supply voltage v dd - 0.5 to 6.0 vdc supply voltage v pc - 0.5 to 6.0 vdc input voltage for digital inputs - 0.3 to (v dd +0.5) vdc storage temperature - 60 to 150c pin voltage (except card interface) - 0.3 to (v dd +0.5) vdc pin voltage (card interface) - 0.3 to (v cc + 0. 5) vdc esd tolerance C card interface pins +/ - 6kv esd tolerance C other pins +/ - 2kv *note: esd testing on smart card pins is hbm condition, 3 pulses, each polarity referenced to ground. note: smart card pins are protected against shorts between any combinations of smart card pins. 12.2 recommended operating conditions p arameter rating supply voltage v dd 2.7 to 5.5 vdc supply voltage v pc 4.75 to 5.5 vdc nds supply voltage v pc 4.85 to 5.5 vdc ambient operating temperature - 40c to +85c input voltag e for digital inputs 0v to v dd + 0.3v 12.3 package thermal parameters package rating 28 so 44 c / w 32qfn 47 c / w (with bottom pad soldered) 32qfn 78 c / w (without bottom pad soldered) 20qfn 53 c / w (with the bottom pad soldered) 20qfn 90 c / w (without the bottom pad soldered)
ds_8024rn_020 73s8024rn data sheet rev. 2 17 12.4 smart card interface requirements symbol parameter condition min typ max unit card power supply (v cc ) regulator general conditions, -40 c < t < 85 c, 4.75v < v pc < 5.5v, 2.7v < v dd < 5.5v nds conditions, 4.85v < v pc < 5.5v v cc card supply voltage including ripple and noise inactive mode - 0.1 0.1 v inactive mode i cc = 1ma - 0.1 0.4 v active mode; i cc <65ma; 5v 4.60 5.25 v active mode; i cc <65ma; 5v, nds condition 4.75 5.25 v active mode; i cc <90ma; 5v 4.55 5.25 v active mode; i cc <90ma; 3v 2.80 3.2 v active mode; single pulse of 1 00ma for 2 s; 5 volt, fixed load = 25ma 4.6 5.25 v active mode; single pulse of 100ma for 2 s; 3v, fixed load = 25ma 2.76 3.2 v active mode; current pulses of 40nas with peak |i cc | <200ma, t <400ns; 5v 4.6 5.25 v active mode; current pulses o f 40nas with peak |i cc | <200ma, t <400ns; 5v, nds condition 4.65 5.25 v active mode; current pulses of 40nas with peak |i cc | <200ma, t <400ns; 3v 2.76 3.2 v v ccrip v cc ripple f ripple = 20k C 200mhz 350 mv i ccmax card supply output current stat ic load current, v cc >4.6 65 ma static load current, v cc >4.55 or 2.7 volts as selected 90 ma i ccf i cc fault current 90 150 ma v sr - v sf v cc slew rate - c f = 3.3 f on v cc 0.02 0.050 0.08 v/ s v srn - v sfn v cc slew rate c f = 1.0 f on v cc nds ap plications 0.06 0.160 0.26 v/ s c f external filter capacitor (v cc to gnd) c f should be ceramic with low esr (<100m ? ). 1 3.3 5 f c fnds external filter capacitor (v cc to gnd) nds applications c f should be ceramic with low esr (<100m ? ). 0.5 1.0 1.5 f
73s8024rn data sheet ds_8024rn_020 18 rev. 2 symbol parameter condition min typ max unit interface requirements C data signals: i/o, aux1, aux2, and host interfaces: i/ouc, aux1uc, aux2uc. i shortl , i shorth , and v inact requirements do not pertain to i/ouc, aux1uc, and aux2uc. v oh output level, hi gh (i/o, aux1, aux2) i oh =0 0.9 v cc v cc +0.1 v i oh = - 40 a 0.75 v cc v cc +0.1 v v oh output level, high (i/ouc, aux1uc, aux2uc) i oh =0 0.9 v dd v dd +0.1 v i oh = - 40 a 0.75 v dd v dd +0.1 v v ol output level, low i ol =1ma 0.3 v v ih input level, high (i/ o, aux1, aux2) 1.8 v cc +0.30 v v ih input level, high (i/ouc, aux1uc, aux2uc) 1.8 v dd +0.30 v v il input level, low - 0.3 0.8 v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i leak input leakage v ih = v cc 10 a i il input current, low v il = 0 0.65 ma i shortl short circuit output current for output low, shorted to v cc through 33 ohms 15 ma i shorth short circuit output current for output high, shorted to ground through 33 ohms 15 ma t r , t f output rise time, fall times for i/o, aux1, aux2, c l = 80pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, cl=50pf, 10% to 90%. 100 ns t ir , t if input rise, fall times 1 s r pu internal pull - up resistor output stable for >200ns 8 11 14 k? fd max maximum data rate 1 mhz t fdio delay, i/o to i/ouc, aux1 to aux1uc, aux2 to aux2uc, i/ouc to i/o, aux1uc to aux1, aux2uc to aux2 (respectively falling edge to falling edge and rising edge to rising edge) edge from master to slave, measured at 50% 60 100 200 ns t rdio 25 90 ns c in input capacitance 10 pf
ds_8024rn_020 73s8024rn data sheet rev. 2 19 symbol parameter condition min typ max unit reset and clock for card interface, rst, clk v oh output level, high i oh = - 200 a 0.9 v cc v cc v v ol output level, low i ol =200 a 0 0.3 v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i rst_lim output current limit, rst 30 ma i clk_lim output current limit, clk 70 ma clk sr3v clk slew rate vcc = 3v 0.3 v/ns clk sr5v clk slew rate vcc = 5v 0.5 v/ns t r , t f output rise time, fall time c l = 35pf for clk, 10% to 90% 8 ns c l = 200pf for rst, 10% to 90% 100 ns duty cycle for clk c l =35pf, f clk 20mhz 45 55 % 12.5 characteristics: digital signals symbol parameter condition min typ max unit digital i/o e xcept for osc i/o v i l input low voltage - 0.3 0.8 v v ih input high voltage 0.7 v dd v dd + 0.3 v v ol output low voltage i ol = 2ma 0.45 v v oh output high voltage i oh = - 1ma v dd - 0.45 v r out pull - up resistor, off 16 21 24 k? | i il1 | input leakage current gnd < v in < v dd - 5 5 a oscillator (xtalin) i/o parameters v ilxtal input low voltage - xtalin - 0.3 0.3 v dd v v ihxtal input high voltage - xtalin 0.7 v dd v dd +0.3 v i ilxtal input current - xtalin gnd < v in < v dd -30 30 a f max max freq. osc or external clock 27 mhz in external input duty cycle limit t r/f < 10% f in , 45% < clk < 55% 48 52 %
73s8024rn data sheet ds_8024rn_020 20 rev. 2 12.6 dc characteristics symbol parameter condition min typ max unit i dd supply current 2.7 7.0 ma i pc supply current v cc on, icc=0 i/o, aux1, aux2=high, clock not toggling 450 650 a i pcoff v pc supply current when v cc = 0 cmdvcc high 345 550 a 12.7 voltage / temperature fault detection circuits symbol p arameter condition min typ max unit v ddf v dd fault (v dd voltage supervisor threshold) no externa l resistor on vddf_adj pin 2.15 2.4 v v pcf v pc fault (v pc voltage supervisor threshold) v pc ds_8024rn_020 73s8024rn data sheet rev. 2 21 13 m echanical drawing (20qfn) 20 1 2 4.0 4.0 2.0 2.0 top view 0.85 nom / 0.90 max 0.02 nom / 0.05 max 0.20 ref seating plane side view pin #1 id r 0.20 k 19 20 2 1 0.50 0.18 / 0.30 0.35 / 0.45 2.50 / 2.70 1.25 / 1.35 2.50 / 2.70 1.25 / 1.35 0.20 min 0.20 min 0.18 / 0.30 bottom view figure 9 : 20qfn mechanical drawing
73s8024rn data sheet ds_8024rn_020 22 rev. 2 14 p ackage pin designation (20 qfn) figure 10 : 20qfn pin out caution: use handling proc edures necessary for a static sensitive component 5 4 3 2 1 20 19 18 17 16 gnd vpc pres pres i/o xtalout teridian 8024rn 5v/ #v clkdiv2 clkdiv1 i/ouc 6 7 8 9 10 cmdvcc gnd clk rst vcc 11 15 14 13 12 xtalin off gnd vdd rstin
ds_8024rn_020 73s8024rn data sheet rev. 2 23 15 m echanical drawing (32qfn) 2.5 5 2.5 5 top view 1 2 3 figure 11 : 32qfn mechanical drawing 0.85 nom. / 0.9max. 0.00 / 0.005 0.20 ref. seating plane side view 0 . 2 min . 0 . 35 / 0 . 45 1 . 5 / 1 . 6 3 . 0 / 3 . 2 0 . 18 / 0 . 3 bottom view 1 2 3 0 . 25 0 . 5 0 . 5 0 . 2 5 3 . 0 / 3 . 2 1 . 5 / 1 . 6 0 . 3 5 / 0 . 4 5 chamfered 0 . 30
73s8024rn data sheet ds_8024rn_020 24 rev. 2 16 p ackage pin d esignation (32qfn) 6 7 8 9 5 4 3 2 1 17 18 19 20 24 23 22 21 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 gnd nc vpc clkstop clklvl pres pres i/o xtalout xtalin off gnd vdd rstin cmdvcc vddf_adj nc aux2 aux1 gnd clk rst vcc nc teridian s8024rn nc nc 5v/ #v clkdiv2 clkdiv1 aux2uc aux1uc i/ouc figure 12 : 32qfn pin out caution: use handling procedures necessary for a static sensitive component
ds_8024rn_020 73s8024rn data sheet rev. 2 25 17 mechanical drawing (so) figure 13: 28 lead so 18 p ackage pin d esignation ( so) (top view) teridian 73s8024rn 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 19 20 28 27 26 25 24 23 22 21 clkdiv1 clkdiv2 5v3v gnd vpc pres pres i/o aux2 aux1 gnd aux2uc aux1uc i/ouc xtalin xtalout off vdd rstin cmdvcc vcc rst clk nc clkstop clklvl vddf_adj gnd figure 14: 28so 73s8024rn pin o ut caution: use handling procedures necessary for a static sensitive component .335 (8.509) .320 (8.128) .420 (10.668) .390 (9.906) .050 typ. (1.270) .305 (7.747) .285 (7.239) .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076) .016 nom (0.40) .110 (2.790) .092 (2.336) pin no. 1 bevel
73s8024rn data sheet ds_8024rn_020 26 rev. 2 19 ordering information part description order no. packaging mark 73s8024rn-sol 28-pin lead-free so 73s8024rn-il/f 73s8024rn-il 73s8024rn-sol 28-pin lead-free so tape / reel 73s8024rn-ilr/f 73s8024rn-il 73s8024rn-32qfn 32-pin lead-free qfn 73s8024rn-im/f s8024rn 73s8024rn-32qfn 32-pin lead-free qfn tape / reel 73s8024rn-imr/f s8024rn 73s8024rn-20qfn 20-pin lead-free qfn 73s8024rn-20im/f 8024rn 73s8024rn-20qfn 20-pin lead-free qfn tape / reel 73s8024rn-20imr/f 8024rn 20 related documentation the following 73s8024rn documents are available from maxim: 73s8024rn data sheet (this document) 73s8024rn combination 28so/20qfn demo board user guide 73s8024rn 28so demo board user?s guide achieving emv electrical compliance with the teridian 73s8024rn dual footprint layout 73s8024rn vs nxp tda8024t implementing the teridian 73s8024rn in nds applications 21 contact information for more information about maxim products or to check the availability of the 73s8024rn, contact technical support at www.maxim-ic.com/support .
ds_8024rn_020 73s8024rn data sheet rev. 2 27 revision history revision date description 1.1 5/18 /200 4 first publication . 1.2 11/5/2004 1.3 4/27/2005 added 20 qfn package option and ordering information. updated 32 qfn order ing information. 1.4 7/15/2005 1.5 8/23/2005 1.6 12/5/2007 removes leaded package options, replaces 32qfn punched with sawn mechanical dimensions, update 28so package dimensions. 1.7 1/17/2008 changed dimension of bottom exposed pad on 32qfn mechanic al package figure. 1.8 1/ 19 /2009 in figure 1 , modified the device block diagram to make pin 2 a no connect. also, changed the pin description. in figure 9 , c hanged the mec hanical drawing for the 20qfn package . added the nds logo to page 1 and assigned document number . added the related documentation and the contact information sections. 1.9 5/27/2010 changed dimension of bottom exposed pad on 32q fn mechanical package figure. 2 6 / 12 corrected the order number s for the 73s8024rn - 32qfn. added maxim logo and contact information . maxim cannot assume responsibility for use of any circuitry other than circuitry entir ely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. m axim integrated products, inc. 160 rio robles , san jose, ca 95134 usa 1 - 408 - 601 - 1000 ? 20 1 2 maxim integrated products is a registered trademark of maxim integrated products inc.

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